It has long been recognized that as the packing density of integrated circuits is increased, the dimensions of the individual elements must be reduced to achieve the high packing density. Thus, the area occupied by each of the drain regions, the source regions, the gate members (and associated channel regions), as well as the contact regions and interconnects must also be significantly reduced in order to achieve the required density. Further, it has been found that, in order to have metal-oxide-semiconductor (MOS) devices operate at high speeds, the high packing density requires that the devices be scaled.
A scaled device, generally, may be defined as a MOS field effect transistor (MOSFET) having a shallow source and drain diffused region, i.e. diffused regions that are less than about 0.6 .mu.m (microns) deep and a small geometry channel length less than about 0.3 micron and probably as close to 1.0 micron or less as possible. Thus, with shallow diffused regions, any process step requiring a contact to be made directly to the diffused region must be done so with extreme care as the shallow nature of the diffused region will allow the contact to spike through the region into the underlying substrate. Additionally, because of the shallow diffused regions, care must be taken to prevent any process step from removing silicon from the diffused region since any excessive thinning of the diffused region will also allow the subsequent metal contact to spike through more readily.